The invention relates to integrated circuit chip testing. Typically, integrated circuit chips are attached to a chip carrier, thermally conductive module chip carrier, circuit card or board, e.g., by solder bonding, controlled collapse chip connect, or the like. For the first time since the wafer was diced, the chip is tested, e.g., electrically tested and logically tested. Some of the tests are subtle, for example tests for active and passive pattern faults and xe2x80x9cstuck at 1xe2x80x9d or xe2x80x9cstuck at 0xe2x80x9d faults. When a fault is found, the chip is removed from the card or board. This is not a simple xe2x80x9cdesolderingxe2x80x9d step, especially in the case of high I/O density integrated circuit chips, bonded with encapsulation chip connect technologies, and usually present in multi-chip modules. When a chip is found to be defective, it must be removed, the chip site redressed, and a new chip installed for testing. In the case of a polymeric substrate, redressing the chip site might include milling.
According to the method of the invention, there is provided a method of testing semi-conductor chips. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier may be the substrate, or a dedicated fixture just for testing chips. This chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts are low contact resistance contacts adapted for holding the integrated circuit chip in place during testing, with low impedance, while allowing easy removal of defective chips and their replacement by other chips.
According to the invention the test fixture contacts have dendritic surfaces. By dendrites are meant essentially vertical members extending outwardly from a generally planar area of conductive material. The dendrites, produced by a columnar growth process, generally have an aspect ratio, of vertical to horizontal dimensions, of at least about 1.0, a height above the planar area of conductive material of about 10 to 100 micrometers.
The chip contacts are brought into conductive contact with the dendrite bearing conductor pads on the chip carrier. Conductive contact requires a low impedance, low contact resistance contact, with the integrated circuit chips being secured from lateral movement with respect to the substrate or fixture. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip.
In the case where the substrate is a temporary test fixture, the chips may be removed from the fixture and either discarded or attached to a suitable substrate. Alternatively, when the chips have been tested in situ, the tested and qualified chips may be bonded through the dendritic conductor pads to the substrate, and the chips which have failed may be removed and discarded without causing need for repair or redressing of the chip site prior to placement of another chip.
In the population of integrated circuit chip carriers, including thermally conductive modules, ceramic substrates, and polymeric substrates, it is necessary to minimize the shipment of modules with defective integrated circuit chips, while minimizing the cost of testing and replacement.
Integrated circuit are subjected to various wafer level tests during various stages of fabrication prior to dicing. However, after dicing it is particularly difficult and expensive to test integrated circuit chips. One reason is that an integrated circuit chip must be tested through its I/O and pads before populating of the carrier, card, board, or the like.
In populating a card, board or other packages integrated circuit chips are attached to a circuit card or board, e.g., by solder bonding, controlled collapse chip connect, wire lead bonding, or the like. The chip is then tested as part of an assembly, e.g., electrically tested and logically tested. Some of the tests are subtle, for example tests for active and passive pattern faults and xe2x80x9cstuck at 1xe2x80x9d or xe2x80x9cstuck at 0xe2x80x9d faults. When a fault is found, the chip is removed from the card or board. This is not a simple xe2x80x9cdesolderingxe2x80x9d step, especially in the case of high I/O density chips, encapsulation chip connect technologies, and multi-chip modules, where the chip must be removed, the chip site redressed, and a new chip installed for testing. In the case of a polymeric substrate, redressing the chip site might include milling.
Dendritic Chip Testers
xe2x80x9cHigh Performance Test Systemxe2x80x9d, IBM Technical Disclosure Bulletin, Volume 33, No. 1A (June 1990), pp 124-125 describes a test system for ULSI integrated circuit memory and logic chips. In the described method, a first silicon wafer xe2x80x9ctest boardxe2x80x9d has metallization complementary to the metallization of the second silicon wafer to be tested. The second silicon wafer has C4 (controlled collapse chip connection) PbSn solder balls on the contacts. The first and second silicon wafers have substantially flat and substantially parallel surfaces, and are said to require a minimum of compressive force for testing.
Anonymous, xe2x80x9cNew Products Test Interposerxe2x80x9d Research Disclosure, January 1990, Number 309 (Kenneth Mason Publications Ltd., England) describes a method for fabricating an interposer-type test head to perform electrical testing of printed circuit cards and boards prior to component assembly. The test interposer is built as a mirror image circuit of the circuit to be tested. However, only the points to be tested, as lands and pads, are present. Circuit lines are not present. The test interposer pads are coated with a dendritic material to make electrical contact to the corresponding points on the printed circuit component to be tested. The circuit board or card and the tester are then brought into contact for testing.
Testers
Compressive type testers are described generally in U.S. Pat. No. 4,716,124 to Yerman et al. for TAPE AUTOMATED MANUFACTURE OF POWER SEMICONDUCTOR DEVICES, U.S. Pat. No. 4,820,976 to Brown for TEST FIXTURE CAPABLE OF ELECTRICALLY TESTING AN INTEGRATED CIRCUIT DIE HAVING A PLANAR ARRAY OF CONTACTS, and U.S. Pat. No. 4,189,825 to Robillard et al. for INTEGRATED TEST AND ASSEMBLY DEVICE.
U.S. Pat. No. 4,189,825 to Robillard et al. for INTEGRATED TEST AND ASSEMBLY DEVICE describes a chip of the beam lead type with sharp points on the substrate leads and etched, conical holes in the semiconductor. The semiconductor and conical holes are metallized with a thin, conformal metal film, leaving conical openings in the metallization. These apertures correspond to the sharp points on the substrate leads. According to Robillard et al, the chips may be assembled and tested, with faulty chips removed and replaced before bonding. Bonding is by ultrasonic welding.
Dendritic Connections
Dendritic connections are described in commonly assigned U.S. Pat. No. 5,137,461 of Bindra et al for SEPARABLE ELECTRICAL CONNECTION TECHNOLOGY. Bindra et al describe separable and reconnectable electrical connections for electrical equipment. Bindra et al""s connectors have dendrites characterized by an elongated, cylindrical morphology. These cylindrical dendrites are prepared by a high frequency, high voltage, high current density, pulse plating methodology utilizing a low metal ion concentration electrolyte. Bindra et al describe the pulsed electrodeposition of Pd from a 10-150 millimolar Pd tetramine chloride, 5 molar ammonium chloride solution at 50 to 450 hertz and 200 to 1100 milliamperes per square centimeter in a pulse plating technique.
Electrodeposition of Pd dendrites is further described in European Patent 0054695 and U.S. Pat. No. 4,328,286 (European Patent 0020020)
U.S. Pat. No. 4,328,286 (European Patent 20020) to Crosby for ELECTROPLATING A SUBSTRATE WITH TWO LAYERS OF PALLADIUM describes producing a low porosity Pd coating for electrical contacts. The Pd coating is prepared by electrodepositing a first layer of Pd from an aqueous bath containing the cationic complex Pd (NH3)4++ and free ammonia with supporting anions (Clxe2x88x92, Brxe2x88x92, NH2SO3xe2x88x92, NO2xe2x88x92 and NO3xe2x88x92) and then electrodepositing a second Pd layer from an aqueous bath containing the anionic complex Pd(NO2)24xe2x88x92 with supporting cations.
Commonly assigned European Patent 54695 (published Jun. 30, 1982, granted Sep. 11, 1985, U.S. application Ser. No. 219,660 filed Dec. 24, 1980) discloses a method of preparing a Pd electrical contact by electrodeposition from a relatively dilute solution that is sprayed onto a cathode which is located completely outside and above the surface of the solution, which is located in a tank. The solution forms a continuous curtain falling from the bottom end of the cathode back into the tank. A higher electric current than usual is used in the deposition process. The dendrites obtained have a larger cross-section than those obtained in conventional processes.
Summary
The art has failed to provide a means for actual or simulated in situ testing of integrated circuit chips, especially xe2x80x9cflip chipsxe2x80x9d, allowing bonding if the chips are satisfactory and replacement of the chips are unsatisfactory.
It is an object of the invention to provide for simulated and actual in situ testing of integrated circuit chips.
It is a further object of the invention to provide a method and apparatus for in situ testing of integrated circuit chips that allows for easy permanent chip attachment of satisfactory chips and easy removal if unsatisfactory chips.
According to the method of the invention, there is provided a method of testing semiconductor chips. The integrated circuit chips are tested under either simulated or actual in situ conditions. In a preferred exemplification the method and apparatus of the invention allows for easy permanent chip attachment of satisfactory chips and easy removal of unsatisfactory chips.
In the method of the invention a chip carrier is provided. The chip carrier may be the substrate or a fixture just for testing chips. This chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces.
The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip and output signal vectors are recovered from the semiconductor chip.
After testing the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.
As used herein, xe2x80x9cdendritesxe2x80x9d are high surface area conductive pads and contacts formed of essentially vertical members extending outwardly from a generally planar area of conductive material. The dendrites, produced by a columnar growth process, generally have an aspect ratio of vertical to horizontal dimensions of at least about 1.0 and a height above the planar area of conductive material of about 10 to 100 micrometers.
The dendritic morphology is obtained by electroplating the underlayer under conditions that give rise to columnar growth; that is, very low metal cation concentration in the electrolyte, with electroplating being carried out at a high voltage, high current, and a high current density. Preferably, the electroplating current is a pulsed current.
The resulting dendrites have a peak height of about 10 to 100 microns and a density (dendrites per unit area) of about 200 to 500 dendrites per square millimeter.
Dendrites have a chip connect pad to dendritic pad contact resistance of about 3 to 5 milliohms.